PSPICE Net list
* CMOS NAND M1 3 1 5 5 PMOS1 M2 3 2 5 5 PMOS1 M3 3 1 4 4 NMOS1 M4 4 2 0 0 NMOS1 C1 3 0 0.05p VCC 5 0 5V VIN1 1 0 0V pulse ( 5 0 1ns 1ns 1ns 40ns 80ns) VIN2 2 0 0V pulse ( 5 0 1ns 1ns 1ns 20ns 60ns) .MODEL NMOS1 NMOS .MODEL PMOS1 PMOS .OP .TRAN 0.5ns 100ns .PLOT TRAN v(1) v(2)+6 v(3)+12 .END .
NAND Logical expression
C =~( A & B ) ;
NAND Truth Table
| A | B | C |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
See Also ...
CMOS NAND Fig.( spice_CMOS-NAND.DXF )
CMOS NAND PSICE Netlist ( spice_CMOS-NAND.txt )
